Yuanchuan Micro closes IDG-led LPU round

Yuanchuan Micro, a startup building inference chips, has closed a Pre-A round of several hundred million yuan. The round was led by IDG Capital, with Futong Capital, Jiukun Venture, Shangqi Capital, Shunxi Fund and Xuhui Science City Investment joining. It is the firm’s fourth raise since the start of 2026, and the money will go to LPU+ chip research, software ecosystem building and product engineering.

Yuanchuan Micro LPU+ inference chip concept
Yuanchuan Micro details its LPU+ inference architecture. (Source: leiphone)

The company was founded in September 2025. Its thesis starts from the agent era: as agents plan, call tools and verify results, a single task can trigger dozens or hundreds of inference steps, and any latency compounds down the chain like a butterfly effect. Chief executive Yang Bin, who spent over twenty years at Huawei building processor teams from scratch and running wireless baseband algorithm and chip work, argues the right chip is derived from a market judgement, not copied from a rival. The architecture he settled on pairs a spatio-temporal compiler with a hard-pipeline design and large-bandwidth SRAM.

Not a Chinese Groq

Yang resists the Groq comparison. Groq’s chip was shaped by the CNN-era models of its birth, he says, whereas Yuanchuan’s LPU+ was designed for the Transformer era from the first line, supporting multimodal models and tuning its data flow for Mixture-of-Experts dynamic scheduling. He borrows a railway metaphor for the compiler: every train’s departure, stop and dwell is planned in advance, so at runtime the chip only executes the timetable. At the 2026 World Artificial Intelligence Conference the design first appeared publicly as an Agentic AI Token Factory, supplying bottom-layer compute for enterprise inference.

Yuanchuan Micro team and roadmap
The Yuanchuan Micro founding team frames the firm around agent-era inference. (Source: leiphone)

The team is the other asset. Chief technology officer Dr Sun has studied GPGPU, GPU and DSP architectures for over thirty years; chief software engineer Will brings more than twenty years of compiler, EDA and heterogeneous systems experience. Yang sums up the launch plainly: a startup is the realisation of everything its founders accumulated. The next round, he says, is already underway.

Editor’s note: This is an adapted translation of the original LeiFeng Network report. It has been trimmed and restructured for readability for an international business audience.

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