Zeng Yi’s office tea was refilled again and again as the conversation unfolded, a typical Guangdong reception: no need to sit stiff, but the matter was clear.
He speaks with a Chaoshan accent, not fast, always finishing a sentence with a smile, eyes narrowing, leaning in, easy to relax around. Talk of AI and RISC-V lights a barely contained excitement.
For two or three years, RISC-V’s domestic momentum has been faster than he expected. Edge and IoT are fully rolled out, especially in Shenzhen and the Greater Bay Area, where many firms are moving from ARM to RISC-V. What excites him more is the AI variable: every tech giant is using RISC-V for custom AI processors, Qualcomm, Google, Meta, no exception. He feels this is RISC-V’s first real big chance.
Sunzhan rides that line. Founded 2022 with about twenty people, it bets on domain-specific architecture, DSA, supplying customers custom CPU, DSP and NPU cores. Zeng Yi spent twenty years in the industry and knows too well that general-purpose processors no longer meet chip and algorithm needs in the post-Moore era.
Three years on, the business truly runs. Asked whether customers fear lock-in, he did not dodge: ‘We want customers on our boat.’ What keeps them, he added, is not lock-in but the value of customisation.
AI is taking the decision over chip architecture
Zeng Yi: AI has greatly changed, even completely broken, the processor-architecture landscape. The decision over chip architecture is shifting. Before, chip firms decided architecture and others wrote programs to it. Now the decision has moved to AI companies. The model decides the architecture.
Previously a customer could run algorithms on an Intel-class general CPU, so the CPU stayed central. But different AI models demand drastically different compute, and a single general CPU cannot serve them efficiently. Early on NVIDIA GPUs bridged it, but as AI moves on-device into smart hardware, a dedicated chip often runs the specific model. At the micro level, the CPU weakens. The vector VPU and tensor TPU/NPU matter more. Their coordination and architecture-instruction optimisation for specific models become the core AI-era need. That is why Intel is hit and ARM’s importance falls.
RISC-V stands out now exactly because those units all need heavy model-facing customisation. Different models need different custom instructions absent or inefficient on closed ARM and Intel. So firms build on RISC-V. This is now consensus: Qualcomm and Tesla acquired RISC-V firms. Google, Meta and even Intel partnered deeply with RISC-V companies, all using open, flexible, modifiable RISC-V as the base of next-generation AI processors.
Zeng Yi: its core advantage is customisability and openness. That freedom to modify is exactly RISC-V’s superiority.
So closed x86 and ARM, which control extension rights, no longer suffice in the AI era. Buying one ARM CPU to run AI models is past. A design integrating multiple units is the substitute.
Zeng Yi: AI’s biggest catalyst is that it platforms chip design. Five to ten years ago a small firm in CPU design was unthinkable. Now CPU designs are everywhere. With a partner we shipped a new CPU in two months thanks to that shift. We already use AI heavily in the engine to generate designs fast, and recently pushed AI into the code-generation engine. Inside I told colleagues we want to be the processor industry’s ‘Claude Code’, using AI to help users auto-generate DSA processors. AI tore down the once-unreachable barrier and spawned massive market opportunity.
RISC-V’s path: not a frontal assault on servers, but reverse penetration via AI
Zeng Yi: the core factor in whether an architecture matures is market demand. Von Neumann won not on technical optimality but on post-war military demand and US adoption. ARM was not born the phone’s best choice. It is also RISC, but the phone’s extreme power sensitivity created demand for a low-power architecture, and that lifted ARM.
RISC-V follows the same law, pushed forward by the AI wave, customisation demand and specialisation. Domestic RISC-V shows two paths: one attacks servers, loud but slow to commercialise. The other attacks DSA, faster to land. More firms entering DSA shows the market choosing.
Zeng Yi: to form a stable three-way split with ARM and x86, RISC-V needs a breakthrough, unlikely from frontal assault on traditional markets. ARM rose not by swallowing Intel’s turf but by catching the phone. RISC-V’s chance is the AI wave: firms build varied AI processors on it, then reverse-penetrate servers, PCs and phones.
On servers, Zeng Yi questions whether that market is even as good as assumed. DPU’s arrival made it less attractive. NPU returns far more. Maybe CPU matters less in future. Devices may not need Windows or Android.
He is not saying CPU loses space, but urges not fixing on one CPU market and returning to demand itself: the need is an overall AI solution, a CPU-VPU-NPU combination with more NPUs. Sunzhan builds a rich shelf of products and integrates them into customer-specific solutions.
On high-performance compute, Zeng Yi: technically RISC-V can reach the top. CAS and Alibaba push it. The gap narrows. But commercial challenge is ecosystem and market acceptance, the real high barrier. Server-chip breakthrough may suit large state-backed firms. Huawei walks that road well.
Fragmentation’s flip side is homogeneity
Zeng Yi: fragmentation is often misread as negative, but it is neutral. ARM’s lack of fragmentation means homogeneity. Firms bought the same public core, even bus and peripherals, paid high licence fees, thin margins. Fragmentation offers differentiation: a customer gained a completely different instruction set and architecture, raised performance, then patented it.
But fragmentation risks: custom instructions need high skill. Poor compiler quality hurts market acceptance and compatibility. Unified test standards and specs, via the working committee, moderately converge it. Sunzhan replaces hand-rolled RTL with a higher-level tool platform: customers define top architecture, tools auto-generate compiler, code and verification.
On the key bottleneck, Zeng Yi: practice. RISC-V’s base is simple, but real use needs much adaptation. Basic software libraries lag ARM’s. He hopes government pushes ecosystem building. On coordination, he praises the domestic RISC-V working committee as a neutral organiser, where socialist strengths help.
Progress is fast. Sunzhan recently opened a DSA computing lab in Shanghai Pudong with the working committee’s guidance, an open platform for firms, institutes, universities and geeks.
On differentiation vs portability, Zeng Yi: customers often want independence and differentiation, not portability. We lower the barrier of processor customisation so customers get differentiated products. Once two engineers per side, two to three months, delivers a full verified package.
On EDA, Sunzhan is the only domestic firm doing both IP and EDA, mirroring Synopsys and Cadence. Its CPU verification reaches 98 to 100 per cent coverage with delivered test code.
On the 2030 forecast that RISC-V reaches a third of the market, Zeng Yi: possible. Our goal is DSA leadership. We already lead this track in China. First-half revenue matches last year’s full year. Full-year doubling is likely. We will firmly raise the DSA flag and have an overseas plan in two years.
Two nodes to break: first, fully AI-ise the customisation tool, truly becoming the semiconductor industry’s Copilot with a known research institute on model optimisation. Second, fight fragmentation with anti-fragmentation, sinking common platforms, the ‘pre-made meals’ of graded AI plans from under 1T to 20-50T to 100-200T compute, and industrial DSP lines against TI’s 2800 and 2900 series.
Editor’s note: This is an adapted translation of the original LeiFengWang report. It has been trimmed and restructured for readability for an international business audience.